The semiconductor industry continuously strives to reduce the size and cost of integrated circuits. With the progressive scaling of feature size and Vdd, there has been a continuous drive and challenge to reduce interconnect capacitance to improve performance, to contain noise and to reduce active power.
One method for measuring the performance of an integrated circuit uses the maximum clock speed at which the circuit operates reliably, which depends on how fast transistors can be switched and how fast signals can propagate. One particular problem confronting the semiconductor industry is that, as integrated circuit scaling continues, the performance improvement is limited by the signal delay time attributable to interconnects in the integrated circuit. According to one definition, integrated circuit interconnects are three-dimensional metal lines with submicrometer cross sections surrounded by insulating material. One definition of an interconnect delay is the product of the interconnect resistance (R) and the parasitic capacitance (C) for the interconnect metal to the adjacent layers. Because of the progressive scaling, the parasitic capacitance (C) has significantly increased due to closer routing of wires, and the interconnect resistance (R) has significantly increased due to a continuous reduction of the wire section.
The following approximations for various generations of integrated circuit technology illustrates this problem. For example, the delay in 0.7 μm technology is about 500 ps, in which about 200 ps seconds are attributable to gate delays and about 300 ps are attributable to interconnect delays. The delay in 0.18 μm technology is about 230 ps, in which about 30 ps are attributable to gate delays and about 200 ps are attributable to interconnect delays. As integrated circuit scaling continues, it is desirable to lower the interconnect RC time constant by using metals with a high conductivity. One high conductivity metal used to lower the RC constant is copper. The use of copper in 0.18 μm technology improves the interconnect delays to about 170 ps. However, even though the delay attributable to the gates continues to decrease as scaling continues beyond the 0.18 μm technology, the overall delay increases significantly because the interconnect delay is significantly increased. It has been estimated that as much as 90 percent of the signal delay time in future integrated circuit designs may be attributable to the interconnects and only 10 percent of the signal delay may be attributable to transistor device delays. As such, it is desirable to lower the interconnect RC time constant by using materials with a low dielectric constant (K) between co-planer and inter-planer interconnects.
Considerable progress has been made in recent years towards developing lower K interlayer dielectric (ILD) using inorganic and organic materials. For example, low-K dense materials are available having a K in a range between 2.5 and 4.1. Additionally, improved processes have been developed using silicon dioxide (SiO2)(K=4) and Polyimide (K=3.7). SiO2-based inorganic dielectrics have been preferred because they provide the thermal and mechanical stability and reliability required for multilevel interconnect integration requirements.
One direction for developing low-K dielectrics incorporates air into dense materials to make them porous. The dielectric constant of the resulting porous material is a combination of the dielectric constant of air (K≈1) and the dielectric constant of the dense material. As such, it is possible to lower the dielectric constant of a low-k dense material by making the dense material porous. Some of the recent developments in ILDs include fluorinated oxide (K=3.5), Spin-On-Glass Hydrogen Silisequioxane (SOG-HSQ) (K=2.7–3.3) and porous siloxane based polymer, also known as Nanoglass (K=2.2–2.3). The fluorination of dielectric candidates, such as Teflon®, achieve a K of about 1.9.
Current research and development is attempting to achieve a dielectric material with a K value around 2 and lower, by incorporating controlled porosity or voids (K=1) in an otherwise dense and mechanically and thermally stable material that is compatible with the interconnect metallurgy and which can be readily integrated with the currently adopted back-end-of-the-line (BEOL) processing and tooling.
Xerogels and Aerogels introduce voids of 5–10 nm in the SOG-HSQ materials to achieve K values less than 2. However, the material compositions and processing are not very reproducible due to the inherent presence of large amount of liquid solvents and non-solvents that need to be removed to create voids and due to shrinkages resulting in internal stress and cracking.
Processes to form porous polymers have been shown in previous work by Farrar (Method Of Forming Foamed Polymeric Material For An Integrated Circuit, U.S. Pat. No. 6,077,792; Method Of Forming Insulating Material For An Integrated Circuit And Integrated Circuits Resulting From Same, U.S. Ser. No. 09/480,290, filed Jan. 10, 2000; Polynorbornene Foam Insulation For Integrated Circuits, Ser. No. 09/507,964, filed Feb. 22, 2000). However, there are some applications where it is desirable to use inorganic porous structures.
The demands placed upon a process for producing a porous structure becomes more stringent as photolithographic dimensions are decreased. Currently, in a damascene metal process, the pores are formed in a layer of insulator prior to etching. Thus, the maximum pore size must be less than the minimum photo dimension, else some of the pores will be located between and connect two trenches. When the metal is deposited in the damascene trenches, the metal fills the pore and forms a short between the lines in two trenches. Thus, if the pores are formed before the metal layer is defined, the pores size distribution should shrink in the same ratio as the minimum feature size. These demands are illustrated in FIGS. 1 and 2.
FIG. 1 illustrates relatively small pores 102 and metal lines 104 and 106 formed in an insulator 108 using a damascene process. The pores 102 are smaller than the photo dimension of the lines 104 and 106. The pores 102 are formed before the metal is deposited, such that the metal 110 flows into some of the pores. However, the pores are small enough so that a short does not form between the metal lines.
FIG. 2 illustrates relatively large pores 202 and metal lines 204 and 206 formed in an insulator 208 using a damascene process. At least some of the pores 202 are larger than the photo dimension of the lines 204 and 206. The pores are formed before the metal is deposited, such that the metal flows into some of the pores. The metal 210 is capable of flowing through a pore and forming a short between the metal lines.
Therefore, there is a need in the art to provide an improved low-K dielectric insulator for interconnects.